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Bhuvaneshwari, S.
- Developing a Sustainable Environment for Improving Computational Efficiency
Abstract Views :162 |
PDF Views:2
Authors
Affiliations
1 Department of Computer Science and Engineering, SNS College of Technology, Coimbatore, Tamil Nadu, IN
1 Department of Computer Science and Engineering, SNS College of Technology, Coimbatore, Tamil Nadu, IN
Source
Data Mining and Knowledge Engineering, Vol 4, No 3 (2012), Pagination: 129-131Abstract
Normally we depend upon computing technologies to perform a task in a better way. It depends on the speed, memory and operational costs of the device performing the task. It should foster a reliable means for performing the tasks. Since, the above mentioned categories can become a drawback and out of 10 tasks at least 7 tasks faces problem. To overcome the problems in the proposed we make use of virtual computing so that it free the memory on individual computer and enables the computer to operate at optimal speeds and provides a new environment for operating systems.Keywords
Computing Technology, Virtual Computing, Operational Costs, Memory, Speed.
- A Review of a Technique for Wide Area Monitoring and Control
Abstract Views :185 |
PDF Views:2
Authors
Affiliations
1 Dr.M.G.R Educational and Research Institute, Chennai, Tamil Nadu, IN
1 Dr.M.G.R Educational and Research Institute, Chennai, Tamil Nadu, IN
Source
Artificial Intelligent Systems and Machine Learning, Vol 7, No 5 (2015), Pagination: 155-158Abstract
The advancement in communication and measurement techniques accelerate the development of wide area monitoring and control, based on the wide area measurement system. In this study, global information of power system will be introduced. By analyzing and computing real-time wide area monitoring and control based on neural network. This method is implemented on the MATLAB.
Keywords
Phasor Measurement Units, Phase Data Concentrator, Neural Network, Global Positioning Satellite System, Wide Area Monitoring and Control System.- PSG ECO-Literacy Scale (Revised 2017)
Abstract Views :229 |
PDF Views:0
Authors
Affiliations
1 Department of Psychology PSG College of Arts & Science, Coimbatore, Tamil Nadu, IN
2 Department of Psychology, PSG College of Arts & Science, Coimbatore, Tamil Nadu, IN
1 Department of Psychology PSG College of Arts & Science, Coimbatore, Tamil Nadu, IN
2 Department of Psychology, PSG College of Arts & Science, Coimbatore, Tamil Nadu, IN
Source
IAHRW International Journal of Social Sciences Review, Vol 5, No 4 (2017), Pagination: 581-587Abstract
An ecosystem is a natural system consisting of all plants, animals (including human), and microorganisms (biotic factors) in an area functioning together with all the non- living physical (abiotic) factors of the environment (Christopherson, 1997). The human population, which has seemingly outbalanced the overall living number on earth, uses/exploits nature to a great extent. Human habits have become unsustainable; touched the boundaries of natural tolerance. Ecologically literate society is a sustainable society which does not destroy the natural environment on which they depend. Being an Eco-literate not only is limited to knowing about one's environment, but also to use the knowledge to live a sustainable living leads ultimately to a sustainable environment. To develop a scale to measure the concept like eco-literacy, an attempt was made and an Eco-Literacy scale that was developed, and validated (Bhuvaneshwari & Naachimuthu, 2016). This first version of the scale is revised with a new dimension of gratitude. The overall reliability of the PSG Eco Literacy scale (revised) is 0.793; test Re-test reliability score for PSG Eco Literacy scale (Revised) is 0.751; Split-half reliability score for PSG Eco Literacy scale (Revised) is 0.882. The new dimension "Gratitude" added to the PSG Eco-Literacy Scale (Revised) increased the reliability value significantly compared to the previous version i.e.0.62to0.75.Keywords
Eco-Literacy, Sustainability, Gratitude.- Comparative Analysis of Pulse Triggered Flip Flop Design for Low Power Consumption
Abstract Views :227 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, IN
1 Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 4, No 2 (2018), Pagination: 584-588Abstract
The advancement in the field of CMOS technology has motivated the research to implement more and more complicated signal processing systems on a Very Large Scale Integrated (VLSI) chip. The basic requirements of such CMOS units are to consume less power and have more functionality. The chip area, speed and power consumption are considered to be the main criteria for evaluating the quality of the systems performance. Hence, there are many types of flip flops designed based on their operation like master and slave based flip flop, conventional transmission gate flip flop and pulse triggered based flip flop. This paper, presents a different methodology using pulse triggered instead of flip flop without altering the existing design style. In this design a pulse triggered flip flop is preferred and then compared with Modified Hybrid Latch Flip Flop (MHLFF), Explicit Pulse Double Edge Triggered Flip Flop (ep-DETFF) and Adaptive Coupling Configured Flip Flop (ACFF). All the proposed flip flops have been designed using 90 nm CMOS technology and their functionality has been verified using micro wind/Dsch2 tool. From this work, the parameters like layout size, transistor count, delay and power are analyzed and compared based on the different types of flip flops. Finally, it is proved that low power Pulse triggered Flip Flop is ACFF.Keywords
Flip-Flop, Pulse Triggered Latch, Modified Hybrid Latch Flip Flop, Adaptive Coupling Configured Flip Flop, Explicit Pulse Double Edge Triggered Flip Flop.References
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